pierce

Pierce Crystal Oscillator Design

Notes: R1 is for power supply isolation.

C1 is an RF bypass for L1.

C4 is an RF bypass for the emitter.

C2 is the phase shift capacitor.

Theory:

The Barkhausen criteria states that for a positive feedback system, oscillation will occur when the loop gain (product of forward gain and feedback gain) has a phase shift of zero (180 degrees for negative feedback systems) and a magnitude of unity. In practical oscillator circuits, the analysis should indicate a loop gain magnitude greater than one, which will cause the amplitude of oscillation to grow exponentially until clipping or other nonlinear phenomena cause the gain magnitude to decrease to unity.

The Pierce oscillator shown above is essentially a common emitter amplifier with a tuned circuit for a collector load and a quartz crystal as a feedback element. In order to determine whether the Barkhausen criteria is satisfied, loop gain must be determined at the frequency of oscillation. This is accomplished by drawing the AC equivalent circuit of the Pierce Oscillator as shown below.

The gain producing action of the transistor in common emitter mode is indicated by the current source having transconductance g_m = 1/r_e= I_E/(.026 v).

The total collector impedance consists of the collector output circuit and the feedback circuit.

The collector output circuit, Z_c, is a tank circuit made up of the tuning coil L1 and tank capacitors C5 and C6 which transform the 50 ohm load up to the some equivalent parallel collector resistance R_L'. Note that near the tank circuit's resonant frequency, the inductive and capacitive reactances nearly cancel, leaving R_L' as the dominant collector load. In practice, the resonant frequency of the tank circuit should be chosen to be approximately 10% lower than the operating frequency of the crystal in order to present a slightly capacitive susceptance. Since the crystal will operate between its series and parallel resonance frequencies, it will present an inductive susceptance. The inductive susceptance of the crystal is reduced slightly by the phase shift capacitor, but the resultant total susceptance is stil inductive, and forms a parallel resonant circuit with the tank circuit which, as mentioned previously, appears capacitive at the crystal frequency.

The feedback circuit consists of the crystal impedance Z_y in series with the transistor base circuit impedance, Z_b.

The crystal impedance can be computed using the equivalent circuit shown below for the crystal.

For the 12 Mhz Crystal, measured values are:

R1 = 12 ohm
L1 = 0.006911H
C1 = 25.45 fF
C2 = 6.6 pF

The base circuit impedance Z_b is the shunt combination of the biasing resistors R2 and R3, the phase shift capacitor C2, and the input impedance of the transistor base which is ßr_e.

The above defined impedances can be used to compute a current divider ratio:

a_i= I_fb/I_c= Z_c/(Z_c + Z_y + Z_b)

which represents the fractional part of the collector current flowing through the feedback path. Now we can write

v_be = I_fbZ_b = a_iI_cZ_b = a_i(-g_mv_be)Z_b

and loop gain is therefore given by

A_L= -a_ig_mZ_b = -g_mZ_bZ_c/(Z_c + Z_y + Z_b)

which must have a phase shift of zero degrees and magnitude greater than unity at the frequency of oscillation.

Output power to the load is determined by the Q point voltages and currents, and total AC collector load resistance at resonance. The zero to peak amplitude of the largest possible AC voltage at the collector is dependent upon whether the the transistor Q-point is closer to saturation or cutoff along its AC load line. Refer to the design notes for Problem 2:13 for help in this determination.

Design Procedure:

1) Select R2, R3, R4 to give a collector current of five to ten milliamps, and an emitter voltage of 2 to 3 volts. This represents the Q point which will be used later in determining the AC load line. Use only standard values for the resistors, and compute predicted values for all voltages and currents using your selected resistor values.

2) Determine required collector AC load resistance to achieve a voltage gain of approximately 100 - 150 for the transistor.

3) Determine values for C5 and C6 which will provide a total capacitance which will resonate with L1 at a frequency approximately 10% below the desired crystal frequency (or overtone), while simultaneously providing the necessary divide ratio to transform the 50 ohm load resistance up to the required collector AC load resistance found in step (2). Use only values which are are available in the lab.

4) Determine the total collector AC resistance based upon your capacitor value selection, draw the AC load line, and determine peak to peak voltage available at the collector when saturation and/or cutoff occurs; calculate the resulting RMS voltage across the 50 ohm load, and load power dissipation.

5 ) Review the design with your instructor and iterate to solve any design shortcomings.

Lab Procedure:

1) Construct the circuit after it has been approved by the instructor. Measure and verify predicted DC operating voltages.

2) Monitor signal level with an oscilloscope and frequency with the frequency counter at the load (50 ohm resistance) while adjusting the tuning core. Record your observations and be prepared to explain the observed behavior.

3) Remove the 50 ohm load and connect the power meter probe to the output. Tune the core for maximum output power, and verify that it is in the neighborhood of your prediction. Continue to monitor frequency and tune for a power level 2-3 db below the maximum.. Attempt to monitor the signal at the transistor collector with the oscilloscope probe, and note any changes in the readings at the output. If oscillation ceases, attempt to retune for oscillation with the scope probe attached, then note any changes at the output when the oscilloscope probe is removed. Repeat this step, attempting to monitor the signal at the base and emitter of the transistor.